As integrated circuits have become larger and more complex, a need has arisen for automated testing. It is economically advantageous to construct VLSI chips on production lines that have a yield less than 100%. Hence, some means for testing the output of these lines must be utilized to identify and remove the inoperative chips. In addition, once these chips are incorporated into larger circuits, testing of the larger circuit is often carried out to identify assembly errors.
A VLSI chip may be viewed as consisting of four broad types of circuitry, signal interfaces, logic circuitry for carrying out the normal functions of the chip, logic circuitry for testing the chip, and registers. The signal interfaces receive signals specifying data and operations to be carried out by the chip. In addition, the signal interfaces output signals representing the results of the operations in question. The registers store various results and are used in the calculations performed by the logic circuitry. In general, the registers are isolated from the signal interfaces by the logic circuitry.
The testing of many of the functions performed by the VLSI chip may be more easily conveniently performed if the contents of the registers can be specified and read without utilizing the logic circuitry to load and read these registers. Hence, special purpose testing logic is routinely included in the chip for accessing the registers. The testing logic typically includes circuits for serial loading and unloading the registers. This logic will be referred to as the scan logic in the following discussion. When the registers are loaded and unloaded using the scan logic, several registers may be connected together by the testing logic to form one long shift register. This long shift register will be referred to as a scan register in the following discussion.
The scan logic typically uses 4 pins on the chip. One pin, referred to as the scan input, is used for reading one bit into the first location of a scan register. A second pin, referred to as the scan output, is used for reading out the bit in the last location in a scan register. The third pin, referred to as the mode pin, is used to specify the scan mode for the VLSI chip. The fourth pin receives clock signals which are used in shift operations.
A scan register is typically loaded by shifting the data into the scan register one bit at a time using the scan input to receive the bits. A typical scan register has thousands of bits. Hence, several thousands of shift instructions must be used to load a scan register.
Similarly, a scan register is read by shifting the data out of the scan register one bit at a time using the scan output. Again, several thousands of shift instructions are typically needed to read out a scan register.
The testing functions including the inputting and outputting of data to and from the scan register, are typically carried out with the aid of general purpose integrated circuit testers. A typical integrated circuit tester includes an interface for making connections to the pins on a VLSI chip or circuit board, a memory for storing the signal levels to be applied to these pins, and a data processor for applying the signals in an order determined by a test specified by the circuit designer. The pin interface typically has provisions for 256 pins. Hence, the signal memory is organized as 256 bit data words. The number of memory words is typically in the millions.
In many existing integrated circuit testers, the signal levels must be specified by these large data words. While these data words are well suited for test functions that must access a large fraction of the pins on a VLSI chip, they are poorly suited for the portion of the test related to loading and unloading scan registers. As noted above, a scan register load operation requires thousands of shift instructions which utilize only 4 pins. Hence, the data words for loading and unloading scan registers require the storage of thousands of 256 bit data words in which only 4 of the 256 bits are utilized. This inefficient utilization of the tester memory can limit the tests that can be performed by these existing testers, since the number of memory words that must be devoted to scan register loading and unloading can be a large fraction of the total memory capacity of the tester.
In principle, additional memory could be added to the tester; however, there is a limit on the total memory that can be used in any given tester. Furthermore, the tester memory must be capable of operation at speeds consistent with those at which the VLSI circuit operates. Hence, the memory must be very fast in addition to being very large. As a result, the cost of the memory is a significant fraction of the cost of an integrated circuit tester. Thus, even if the tester memory could be expanded to accommodate the instructions needed to load and unload the scan registers, this approach is economically disadvantageous.
This inefficient use of the tester memory has led to new tester designs in which the memory is divided into words of different length. These testers include a very large number of short data words, e.g. 4 bit data words, for storing the scan instructions. While this approach provides an economically satisfactory solution to the memory efficiency problem, it requires the user to purchase a new tester. The cost of a VLSI tester is many millions of dollars. Hence, it would be advantageous to provide a solution to memory efficiency problem that does not require the user to purchase a new tester.
Broadly, it is an object of the present invention to provide an improved VLSI circuit design which is better adapted to test procedures utilizing scan registers.
It is a further object of the present invention to provide a VLSI circuit design that more efficiently utilizes the memory of existing VLSI testers.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the present invention and the accompanying drawings.